User Interface Signals - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English

The user interface provides an interface for you to send commands to the controller and receive the response for the same. The number of commands per user clock accepted by the interface depends on Burst Length (BL) of the memory device. For BL2, four commands per user clock is supported because the user clock to the memory clock ratio is 1:4. Therefore in one user clock, four memory clock transactions are possible. Similarly for BL4 two commands per user clock and for BL8 one command per user clock is supported. The commands per user clock for the BL2 and BL4 can be a mix of write and read commands. With a clock ratio of 1:4, there can be four independent command channels for BL2 and two independent command channels for BL4. Each channel can accept any command to any address location. Each channel processes and responds to its commands in the order it was received.

The user interface provides a set of signals used to issue a read or write command to the memory device. These signals are summarized in the table.

Table 1. User Interface Signals
Signal I/O Width Description
sys_clk_p/n I 1 Primary clock to IP
sys_rst I 1 Primary Active-High reset to IP
user_cmd_en I 1 Indicates commands, address, and bank address are valid at the input.
user_cmd I If AMUX ON or BL = 2: width = 2x2 Else: width = 2xCMD_PER_CLK Command input
  • 2'b01 - Write
  • 2'b10 - Read
  • 2'b00 - NOP
user_addr I ADDR_WIDTH x CMD_PER_CLK Memory Address corresponding to user_cmd.
user_ba I BANK_WIDTH x CMD_PER_CLK Memory Bank Address corresponding to user_cmd.
user_wr_en I CMD_PER_CLK Per command channel indication of valid user_wr_data and user_wr_dm when asserted.
user_wr_data I MEM_DQ_WIDTH x BL x CMD_PER_CLK Write data corresponding to write command on the respective channel.
user_wr_dm I MEM_DM_WIDTH x BL x CMD_PER_CLK Write data mask corresponding to write command on the respective channel. Top-level parameter DM_EN must be set to 1 to enable Data Mask support.
user_afifo_empty O CMD_PER_CLK When asserted indicates CMD/Address FIFO is empty.
user_afifo_aempty O CMD_PER_CLK When asserted indicates CMD/Address FIFO is almost empty.
user_afifo_full O CMD_PER_CLK When asserted indicates CMD/Address FIFO is full.
user_afifo_afull O CMD_PER_CLK When asserted indicates CMD/Address FIFO is almost full.
user_wdfifo_empty O CMD_PER_CLK When asserted indicates Write Data FIFO is empty.
user_wdfifo_aempty O CMD_PER_CLK When asserted indicates Write Data FIFO is almost empty.
user_wdfifo_full O CMD_PER_CLK When asserted indicates Write Data FIFO is full.
user_wdfifo_afull O CMD_PER_CLK When asserted indicates Write Data FIFO is almost full.
user_rd_valid O CMD_PER_CLK When asserted indicates user_rd_data is valid on respective channels.
user_rd_data O MEM_DQ_WIDTH x BL x CMD_PER_CLK Read data corresponding to read command issued on respective channels.
init_calib_complete O 1 When asserted indicates completion of memory initialization and memory interface calibration.
ui_clk O 1 User interface clock that is 1/4 of RLDRAM 3 clock.
ui_clk_sync_rst O 1 Active-High user interface reset
calib_error O 1 When asserted indicates error during calibration.
dbg_clk O 1 Debug clock. Do not connect any signals to dbg_clk and keep the port open during instantiation.