Write Latency Calibration - 1.0 English

1. In this stage, a single write command with a write latency of 0 is issued to different banks with a data pattern: 0xffffffff, 0x00000000, 0x00000000, 0x00000000, and 0xffffffff.
2. Reads are continuously issued to locations where zeros are written. Because the read latency calibration has not been performed, read latency is set to a large value so that data is properly read.
3. An incorrect write latency results in 1s in the read data. Write latency is incremented by 1 until the read data is all 0s.
4. Repeat the same steps with the write pattern: 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, and 0x00000000.
5. When read data is all 1s, this stage is complete.