If the GCIO pin and XPLL are not allocated in the same bank, the CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. To use the BACKBONE route, BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV must be instantiated between GCIO and XPLL input. QDR-IV SRAM manages these constraints for designs generated with the Reference Input Clock option selected as Differential (at ). Also, QDR-IV SRAM handles the IP and example design flows for all scenarios.
If the design is generated with the Reference Input Clock option selected as No Buffer (at ), the CLOCK_DEDICATED_ROUTE constraints and BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV instantiation based on GCIO and XPLL allocation needs to be handled manually for the IP flow. QDR-IV SRAM does not generate clock constraints in the XDC file for No Buffer configurations and you must take care of the clock constraints for No Buffer configurations for the IP flow.
For an example design flow with No Buffer configurations, QDR-IV SRAM generates the example design with differential buffer instantiation for system clock pins. QDR-IV SRAM generates clock constraints in the example_design.xdc. It also generates a CLOCK_DEDICATED_ROUTE constraint as the “BACKBONE” and instantiates BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV between GCIO and XPLL input if the GCIO and XPLL are not in same bank to provide a complete solution. This is done for the example design flow as a reference when it is generated for the first time.
If in the example design, the I/O pins of the system clock pins are changed to some other pins with the I/O pin planner, the CLOCK_DEDICATED_ROUTE constraints and BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV instantiation need to be managed manually. A DRC error is reported for the same.