Command Order to the Memory - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

The following figure shows the command order when there is no command switch from read to write (vice-versa) and no bank collision. PORT A is called first by the controller followed by PORT B. This gets repeated in the same method.

Figure 1. Command Order