Command Sequence - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

Because the read and write latencies are different for the given memory, the user interface ensures that the read and write command sequence issued at the memory are in correct order. If this is not guaranteed by the user interface, the device might be defective as the data bus in case of QDR-IV memory is bidirectional. Suppose for a given memory device, the read latency is eight and write latency is five.

For example, if you issued one read command followed by three write commands on the four channels. This means that from the time when a read command is executed, eight memory clocks are required to retrieve the read data. On the eighth clock, memory drives the data bus. Because there are following write commands, the Versal ACAP tries to drive the data bus on the sixth, seventh, and eighth cycle.

On the eighth cycle, there is a case where both the Versal ACAP and the memory tries to drive the same bus. This might damage the device and hence it is taken care of by the user interface inserting NOPs. This is explained further in the following table (W stands for a write command, R stands for a read command, NOP stands for No Operation).

Table 1. Command Sequence
Input Command from User Interface

CH0, CH1, CH2, CH3

Output Command from User Interface to Memory Interface
WR-WR-WR-WR WR-WR-WR-WR
RD-RD-RD-RD RD-RD-RD-RD
WR-RD-WR-RD WR-RD-NP-NP-NP-NP-NP-NP-NP-NP-WR-RD
RD-WR-RD-WR RD-NP-NP-NP-NP-NP-NP-NP-NP-WR-RD-NP-NP-NP-NP-NP-NP-NP-NP-WR