Constraining the Core - 1.0 English

Required Constraints

The QDR-IV SRAM Vivado IDE generates the required constraints. A location constraint and an I/O standard constraint are added for each external pin in the design. The location is chosen by the Vivado IDE according to the banks and byte lanes chosen for the design.

The I/O standard is chosen by the memory type selection and options in the Vivado IDE and by the pin type. A sample for qdriv_a[0] is shown here.

set_property PACKAGE_PIN AK26 [get_ports {a[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {a[0]}]

The system clock must have the period set properly:

create_clock -name sys_clk_i -period 2.000 [get_ports sys_clk_p]

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Clock Frequencies

This section is not applicable for this IP core.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

The QDR-IV SRAM tool generates the appropriate I/O standards and placement based on the selections made in the Vivado IDE for the interface type and options.