Core Overview - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

The QDR-IV SRAM is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports.

The QDR-IV core is a physical layer with a controller for interfacing Versal ACAP user designs to the QDR-IV devices. QDR-IV SRAMs offer high-speed data transfers on separate read and write buses on the rising and falling edges of the clock. These memory devices are used in high-performance systems as temporary data storage, such as:

  • Look-up tables in networking systems
  • Packet buffers in network switches
  • Cache memory in high-speed computing
  • Data buffers in high-performance testers

The QDR-IV SRAM solutions core includes a PHY and the controller that takes user commands, processes them to make them compatible to the QDR-IV protocol, and provides the converted commands to the QDR-IV memory. The controller inside the core enables you to provide four commands per cycle simultaneously.

The QDR-IV core includes the hard blocks inside the Versal ACAP and the soft calibration logic necessary to ensure optimal timing of the hard blocks interfacing to the memory part.

The hard blocks include:

  • Data serialization and transmission
  • Data capture and deserialization
  • High-speed clock generation and synchronization
  • Coarse and fine delay elements per pin with voltage and temperature tracking

The soft blocks include:

Memory Initialization
The calibration modules provide an initialization routine and a reset sequence for the particular memory type.

The QDR-IV must be initialized before it can operate in the normal functional mode. Initialization uses four special pins:

  • RST_n pin to reset the device.
  • CFG_n pin to program the configuration registers
  • LBK0_n and LBK1_n pins for the loopback function.

The following steps should be followed to initialize the QDR-IV memory:

  1. Apply power to the QDR-IV. Follow instructions described in the power-up sequence section in the memory data sheet.
  2. Apply reset to the QDR-IV. Follow reset sequence instruction in the memory data sheet.
  3. Assert Config (CFG_n = 0) and program the impedance control register.
  4. Because the input impedance is updated, allow the XPLL time (tXPLL) to lock to the input clock.
Calibration
The calibration modules provide a complete method to set all delays in the hard blocks and soft IP to work with the memory interface. Each bit is individually trained and then combined to ensure optimal interface performance. Results of the calibration process are available through the Xilinx debug tools. After completion of calibration, the PHY layer presents the raw interface to the memory part.

The following figure shows a high-level block diagram of the QDR-IV interface solution.

Figure 1. Versal ACAP Memory Interface Solution