The following section focuses on your command sequence and the controller after handling the command switching/collision processes and distributing to the memory interface.
In the first case, the command sequence is located at the input and output of the controller when there is no collision. The PORT A command has switched from read to write. As explained in the earlier section, the data bus is common for read and write and it has to switch direction. Therefore, it has to wait for the read command to be completed.
The controller introduces eight NOPs on PORT A to avoid the bus contention at the memory interface (see the following figure). Because the write latency of the memory device is less than the read latency when the command switches from write to read, the controller inserts four NOPs between the commands. All PORT A commands are sent on the rising edge of the memory clock (CK clock shown in figure) and all PORT B commands are sent on the falling edge.
In the second case, there is a collision between the channel 0 of PORT A and PORT B, but there is no command switching. The collision on PORT B results in its command processing getting delayed by one user clock. The controller now serves the next PORT A command to avoid bank rule violation at the memory. This is shown in the following figure where the rising edge on all PORT A commands are sent to the memory, but on the falling edge. Four NOPs are inserted first and then pending PORT B commands.
Finally, the next and worst case is when there are bank collision and command switching. First, PORT B has a collision and its execution is delayed by one clock. After one clock when the controller serves the PORT B command, the next command on PORT A is a write which is a command switch. This is seen in the following figure where four NOPs are inserted on PORT B because of the collision and eight NOPs are inserted on PORT A for read to write command switching.
