- Component support for interface widths up to 36 bits
- Single component interface with x18 and x36 memory device support
- 2-word burst support (BL2 only)
- Only POD12 standard support
- Memory device support with 72 Mb density and 144 Mb density
- Support for 5 (for HP memory part) and 8 (for XP memory part) cycles of read latency
- Support for 3 (for HP memory part) and 5 (for XP memory part) cycles of write latency
- Source code delivery in Verilog and SystemVerilog
- 4:1 memory to Versal ACAP logic interface clock ratio
- Interface calibration and training information available through the Vivado® hardware manager
- Programmable On-die Termination (ODT) support for address, clock, and data