QDR-IV SRAM I/O pin planning is completed with the full design pin planning using the Vivado I/O Pin Planner. QDR-IV SRAM I/O pins can be selected through several Vivado I/O Pin Planner features including assignments using I/O Ports view, Package view, or Memory Bank/Byte Planner. Pin assignments can additionally be made through importing an XDC or modifying the existing XDC file.
These options are available for all QDR-IV SRAM designs and multiple QDR-IV SRAM IP instances can be completed in one setting. To learn more about the available Memory IP pin planning options, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).