The PHY executes a QDR Consortium compliant QDR-IV initialization sequence after the completion of BISC. Each QDR-IV SRAM has a series of configuration registers accessed through configuration mode. These configuration registers determine various SRAM behaviors, such as ODT, impedance, address inversion, and data inversion. Memory IP designs do not issue a calibration failure during Memory Initialization.
All other calibration stages are reviewed in the following Debugging Calibration Stages section.