Memory Initialization and Calibration Sequence - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

After deassertion of the system reset, the PHY performs some required internal calibration steps first.

  1. The built-in self-calibration (BISC) of the PHY is run. It is used to compensate the internal skews among the data bits and the strobe on the read path. The computed skews are used in the voltage and temperature tracking after calibration is completed.
  2. After BISC is completed, calibration logic performs the required power-on initialization sequence for the memory. This is followed by several stages of timing calibration for the write and read datapaths.
  3. After calibration is completed, the PHY calculates internal offsets to be used in voltage and temperature tracking.
  4. When the PHY indicates the calibration completion, the user interface command execution begins.

The following figure shows the overall flow of memory initialization and the different stages of calibration.

Figure 1. PHY Overall Initialization and Calibration Sequence