The PHY is considered the low-level physical interface to an external QDR-IV SRAM device. It contains the entire calibration logic for ensuring reliable operation of the physical interface itself. The PHY generates the signal timing and sequencing required to interface to the memory device.
The PHY contains the following features:
- Clock/address/control-generation logics
- Write and read datapaths
- Logic for initializing the QDR-IV SRAM after power-up
In addition, the PHY contains calibration logic to perform timing training of the read and write datapaths to account for system static and dynamic delays.