Project-Based Simulation - 1.0 English

Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)

Document ID
PG355
Release Date
2021-12-03
Version
1.0 English

This method can be used to simulate the example design using the Vivado Design Suite (IDE). Memory IP delivers IEEE encrypted memory models for QDR-IV.

The Vivado simulator, Questa Advanced Simulator, IES, and VCS tools are used for QDR-IV IP verification at each software release. The Vivado simulation tool is used for QDR-IV IP verification from 2021.2 Vivado software release. The following subsections describe steps to run a project-based simulation using each supported simulator tool.