The sys_rst
signal resets the entire
memory interface design which includes general interconnect (fabric) logic, RIU
interface logic, MicroBlaze, and calibration logic.
The sys_rst
input signal is synchronized internally to
create the qdriv_rst_clk
signal. The qdriv_rst_clk
reset signal is synchronously asserted and
synchronously deasserted.
The following figure shows the qdriv_rst_clk
signal (fabric reset) is synchronously asserted with a few
clock delays after the sys_rst
signal is asserted. When
the qdriv_rst_clk
signal is asserted, there are a few
clocks before the clocks are shut off.
Figure 1. Reset Sequence Waveform
The following are the reset sequencing steps:
- Reset to design is initiated after the
qdriv_rst_clk
signal goes High. - The
qdriv_rst_clk
signal goes Low when theqdriv_rst_clk
signal is High. - Reset to design is deactivated after the
qdriv_rst_clk
signal is Low. - After the
qdriv_rst_clk
signal is deactivated, theinit_calib_complete
signal is asserted after calibration is completed.