There is a limitation for PORT B to access a bank at next edge after the bank is accessed by PORT A. There must be 1.5 memory clock gaps between the access of a bank by PORT B and PORT A if the bank access is followed by PORT B.
If you assert the same bank for PORT A and PORT B, the controller delays the command from PORT B by 1.5 memory clock cycles and asserts a busy until the execution of all the commands get completed.