- XPLL is used to generate the Versal ACAP logic system clock (1/4 of the memory clock)
- Must be located in the center bank of memory interface
- CLKOUTPHY from XPLL drives XPHY within its bank
- Must use internal feedback
Note: XPLLs do not have fractional clock generation.
The following figure shows an example of the clocking structure for a three bank memory interface. The GCIO drives the XPLL located at the center bank of the memory interface. The XPLL in the center bank drives the inputs of the XPLLs in each of the adjacent banks.
Figure 1. Clocking Structure for Three Bank Memory Interface
