The ILA core is designed to be used in an application that requires verification or debugging using AMD Vivado™ . The following figure shows CIPS IP core writes and reads from the AXI block RAM controller through the AXI Network on Chip (NoC). The ILA core is connected to the interface net between the AXI NoC and AXI block RAM controller to monitor the AXI4 transaction in the hardware manager.
Figure 1. AXI Interface Debugging Use Case
