ILA Core and Timing Considerations - 1.2 English

Integrated Logic Analyzer (ILA) with AXI4-Stream Interface LogiCORE IP Product Guide (PG357)
Document ID
PG357
Release Date
2023-11-01
Version
1.2 English

The configuration of the ILA core has an impact in meeting the overall design timing goals. Follow the recommendations below to minimize the impact on timing:

  • Choose probe width judiciously. The bigger the probe width the greater the impact on both resource utilization and timing.
  • Choose ILA core data depth judiciously. The bigger the data depth, the greater the impact on both block RAM resource utilization and timing.
  • Ensure that the clocks chosen for the ILA cores are free-running clocks. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
  • Close timing on the design prior to adding the debug cores. AMD does not recommend using the debug cores to debug timing related issues.
  • Make sure the clock input to the ILA core is synchronous to the signals being probed. Failure to do so results in timing issues and communication failures with the debug core when the design is programmed into the device.
  • Make sure that the design meets timing before running it on hardware. Failure to do so results in unreliable results.
  • If the design does not meet the timing requirements after adding debug cores and the timing failure is in the ILA or AXIS-ILA core, try increasing the number of input pipeline stages (C_INPUT_PIPE_STAGES).
  • If the design does not meet the timing requirements after adding debug cores and the timing failure is in the ILA or AXIS-ILA core, try a different implementation strategy such as Performance_Explore or Performance_ExtraTimingOpt.
  • If the design does not meet the timing requirements after adding debug cores and the timing failure is in the AXIS-ILA core, try changing the storage target to UltraRAM (URAM). This can ease the timing requirement for block RAM (BRAM) control signals.
  • If a timing failure is observed after adding debug cores, try using a clock with a frequency between 100 MHz and 250 MHz for the clock connected to the AXI4-Debug Hub. This will ease the timing requirements for imposed on the AXI-Streaming connectivity for all debug cores connected to the AXI4-Debug Hub.