|
Core Specifics |
| Supported Device Family
1
|
Versal®
ACAP |
| Supported User Interfaces |
IEEE Standard 1149.1 – JTAG |
| Provided with
Core
|
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx®
Design Constraints
(XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
Not Provided |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change
Logs |
Master Vivado IP Change
Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|