The Integrated Logic Analyzer (ILA) with AXI4-Stream Interface core is a customizable logic analyzer IP which can be used to monitor the internal signals and interfaces of a design. The ILA core includes many advanced features of modern logic analyzers, including boolean trigger equations and edge transition triggers. The core also offers interface debugging and monitoring capability along with protocol checking for memory mapped AXI and AXI4-Stream. Because the ILA core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components of the ILA core. To debug interfaces within a design, ILA IP needs to be added to a block design in the Vivado® IP intergrator. Similarly, AXI4/AXI4-Stream protocol checking option can be enabled for ILA IP in the IP integrator. Protocol violations can be then displayed in the waveform viewer of Vivado logic analyzer.