When building a platform that will use the AI Engine IP, by default, the AI Engine has only one enabled memory-mapped AXI port for configuration. The rest of the interface ports are enabled and connected using the Vitis™ software platform linker v++. Changing additional interface ports from the AI Engine IP is not supported as they could result in undesirable behavior such as compilation or runtime failures.
For more information on AI Engine programming, refer to the Versal ACAP AI Engine Programming Environment User Guide (UG1076).
Connect the input S00_AXI port of the AI Engine IP to the AXI NoC.
The following figure shows the available configuration settings.
- Component Name
- Shows the unique name for the AI Engine IP core and can only be changed through the Block properties in Vivado IP integrator.
- AIE PLL Reference Frequency (MHz)
- Selects the reference clock for the AI Engine IP PLL. The clock frequency depends on the .
- AI Engine Core Frequency (MHz)
- Selects the AI ENGINE PLL output clock to the AI Engine IP Array.