The Xilinx® LogiCORE™ AI Engine IP enables the configuration of the AI Engine Array Interface. This array is connected to the Network on Chip and to the programmable logic (PL) through tiles that are located in the AI Engine Array Interface. This IP allows the specification of the number of AXI4-Stream and memory mapped AXI interfaces with their respective width and direction and defines the clock driving the AI Engine array.
For detailed information on the Versal™ ACAP AI Engine, refer to the Versal ACAP AI Engine Architecture Manual (AM009).