There is no reset signal being driven from the PL. The reset signal is generated internally within the IP. There is a 10-bit counter present, and the reset signal is initially low. When all of the counter's bits become high (i.e., after 1024 clock cycles), the reset signal becomes high which deasserts the active low reset. So, after an initial 1024 clock cycles, all the registers present inside the IP come out of the reset state.