The following table shows the S**_AXI Interface Ports and their descriptions.
Port Name | I/O | Description |
---|---|---|
s**_axi_awaddr (C_S**_AXI_ADDR_WIDTH – 1: 0) |
I | Write Address Channel Address Bus |
s**_axi_awid (C_S**_AXI_ID_WIDTH – 1: 0) |
I | Write Address Channel ID |
s**_axi_awuser (C_S**_AXI_AWUSER_WIDTH – 1: 0) |
I | Write Address Channel user |
s**_axi_awlen[7:0] | I | Write Address Channel Burst Length. In data beats – 1. |
s**_axi_awsize[2: 0] | I | Write Address Channel Burst Size. Indicates width of burst
transfer.
|
s**_axi_awburst[1:0] | I | Write Address Channel Burst Type. Indicates type burst.
|
s**_axi_awprot[2:0] | I | Write Address Channel Protection. This is always driven with a constant output of 0010b. |
s**_axi_awlock | I | Write Address Channel exclusive access. |
s**_axi_awqos[3:0] | I | Write Address Channel QoS |
s**_axi_awregion[3:0] | I | Write Address Channel Region |
s**_axi_awcache[3:0] | I | Write Address Channel Cache |
s**_axi_awvalid | I | Write Address Channel Write Address Valid. Indicates if
m**_axi_awaddr is valid.
|
s**_axi_awready | O | Write Address Channel Write Address Ready. Indicates target is
ready to accept the write address.
|
s**_axi_wdata (C_S**_AXI_DATA_WIDTH – 1:0) |
I | Write Data Channel Write Data Bus |
s**_axi_wstrb (C_S**_AXI_DATA_WIDTH/ 8 – 1:0) |
I | Write Data Channel Write Strobe Bus. Indicates which bytes are valid in the write data bus. This value is passed from the stream side strobe bus. |
s**_axi_wuser (C_S**_AXI_WUSER_WIDTH – 1: 0) |
I | Write Data Channel user |
s**_axi_wlast | I | Write Data Channel Last. Indicates the last data beat of a
burst transfer.
|
s**_axi_wvalid | I | Write Data Channel Data Valid. Indicates m**_axi_wdata is
valid.
|
s**_axi_wready | O | Write Data Channel Ready. Indicates the write channel target is
ready to accept write data.
|
s**_axi_bresp[1:0] | O | Write Response Channel Response. Indicates results of the write
transfer.
|
s**_axi_bvalid | O | Write Response Channel Response Valid. Indicates response, m**_axi_bresp, is valid. 0 = response is not valid 1 = response is valid |
s**_axi_bid (C_S**_AXI_ID_WIDTH – 1: 0) |
O | Write Response Channel ID |
s**_axi_buser (C_S**_AXI_BUSER_WIDTH – 1: 0) |
O | Write Response Channel user |
m**_axi_bready | I | Write Response Channel Ready. Indicates write channel is ready
to receive response.
|
s**_axi_araddr (C_S**_AXI_ADDR_WIDTH – 1:0) |
I | Read Address Channel Address Bus |
s**_axi_arid (C_S**_AXI_ID_WIDTH – 1: 0) |
I | Read Address Channel ID |
s**_axi_aruser (C_S**_AXI_ARUSER_WIDTH – 1: 0) |
I | Read Address Channel user |
s**_axi_arlen[7:0] | I | Read Address Channel Burst Length. In data beats – 1. |
s**_axi_arsize[2:0] | I | Read Address Channel Burst Size. Indicates width of burst
transfer.
|
s**_axi_arburst[1:0] | I | Read Address Channel Burst Type. Indicates type burst.
|
s**_axi_arprot[2:0] | I | Read Address Channel Protection. This is always driven with a constant output of 0010b. |
s**_axi_arcache[3:0] | I | Read Address Channel Cache |
s**_axi_arlock | I | Read Address Channel exclusive access. |
s**_axi_arqos[3:0] | I | Read Address Channel QoS |
s**_axi_arregion[3:0] | I | Read Address Channel Region |
S**_axi_arvalid | I | Read Address Channel Read Address Valid. Indicates if
m**_axi_araddr is valid.
|
s**_axi_arready | O | Read Address Channel Read Address Ready. Indicates target is
ready to accept the read address.
|
s**_axi_rdata (C_S**_AXI_DATA_WIDTH – 1:0) |
O | Read Data Channel Read Data Bus |
s**_axi_rid (C_S**_AXI_ID_WIDTH – 1: 0) |
O | Read Data Channel ID |
s**_axi_ruser (C_S**_AXI_RUSER_WIDTH – 1: 0) |
O | Read Data Channel user |
s**_axi_rlast | O | Read Data Channel Last. Indicates the last data beat of a
burst transfer.
|
s**_axi_rvalid | O | Read Data Channel Data Valid. Indicates m**_axi_rdata is
valid.
|
s**_axi_rready | I |
Read Data Channel Ready
|
s**_axi_rresp[1:0] | O | Read Response Channel Response. Indicates results of the write
transfer.
|