Clocking - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

Document ID
PG361
Release Date
2020-12-11
Version
2.0 English
Revision

The aclk input port is used as clock port on the AXI interface by the AXI4 Debug Hub. All of the AXI signals are generated or sampled based on the rising edge of the aclk. You must connect this to the proper clock source in the design.