The Debug Hub provides an interface between Vivado® Hardware Manager tool and up to 64 debug cores (such as ILA and VIO) via JTAG or HSDP debug interfaces of the target Versal™ device.
The Debug Hub IP provides AXIS interface for connectivity to debug cores while an AXI interface attaches it to Network-on-Chip or other type of AXI master interfaces.
Figure 1. Debug Hub
