Customizing and Generating the Core or Subsystem - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

Document ID
PG361
Release Date
2020-12-11
Version
2.0 English
Revision

This section includes information about using Xilinx® tools to customize and generate the core or subsystem in the Vivado® Design Suite.

If you are customizing and generating the core or subsystem in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core or subsystem using the following steps:

  1. Select the IP from the IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

The following figure shows the view of IP catalog. AXI4 Debug Hub will be listed in the Debug and Verification category in the Debug sub-category.
Note: This IP will only be visible if a Versal device is selected as this IP is only supported on Versal architectures.
Figure 1. AXI Debug Hub Core in Vivado IP Catalog

The following figure shows the Customize GUI/ Wizard when you click AXI4 Debug Hub in the Vivado IP Catalog. The various configuration options are explained below

Figure 2. Axi4 Debug Hub Customize IP Window
Component Name
Use this text field to provide a unique module name for the core.
Number of Debug Cores
Selects the number of debug cores to be connected to Debug Hub. Valid range for this parameter is from 0 to 64.
AXI Data Width
Configures AXI Data Width according to the master. It is by default set to Auto, it can be set manually.
AXI Address Width
Configures AXI Address Width according to the master. It is by default set to Auto, it can be set manually.
AXI ID Width
Configures AXI ID Width according to the master. It is by default set to Auto, it can be set manually.