This section includes information about using Xilinx® tools to customize and generate the core or subsystem in the Vivado® Design Suite.
If you are customizing and generating
the core or subsystem in the
Vivado IP integrator, see
Vivado Design Suite User Guide: Designing
IP Subsystems using IP Integrator (UG994) for
detailed information. IP integrator might auto-compute certain
configuration values when validating or generating the design. To
check whether the values do change, see the description of the
parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core or subsystem using the following steps:
- Select the IP from the IP catalog.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.
The following figure shows the Customize GUI/ Wizard when you click AXI4 Debug Hub in the Vivado IP Catalog. The various configuration options are explained below
- Component Name
- Use this text field to provide a unique module name for the core.
- Number of Debug Cores
- Selects the number of debug cores to be connected to Debug Hub. Valid range for this parameter is from 0 to 64.
- AXI Data Width
- Configures AXI Data Width according to the master. It is by default set to Auto, it can be set manually.
- AXI Address Width
- Configures AXI Address Width according to the master. It is by default set to Auto, it can be set manually.
- AXI ID Width
- Configures AXI ID Width according to the master. It is by default set to Auto, it can be set manually.