IP Facts - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

Document ID
Release Date
2.0 English
LogiCORE™ IP Facts Table
Core or Subsystem Specifics
Supported Device Family 1 Versal™ ACAP
Supported User Interfaces AXI4 and AXI4 Stream
Provided with Core or Subsystem
Design Files Encrypted RTL
Example Design Verilog
Test Bench Not Provided
Constraints File XDC
Simulation Model Not provided
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation Not supported
Synthesis Vivado Synthesis
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.