Interface Ports - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

Document ID
PG361
Release Date
2020-12-11
Version
2.0 English
Revision
Table 1. Interface Ports
Port Name I/O Description
aclk I Input clock at which all the interfaces of this block will be synced and working
aresetn I Input reset for this block, at which all the things inside would be reset
S_AXI I Input interface, used for the host side, for driving the transactions or data from or to the host
Sxx_AXIS I Slave AXIS input to take the read data from the debug cores, such as AXIS_ILA or VIO
Mxx_AXIS O Master AXIS output to give the write data to the debug cores, such as AXIS_ILA or VIO
Note: The Sxx_AXIS and Mxx_AXIS in the table above shows the S_AXIS and M_AXIS interfaces from the IP. The subscript XX denotes the number of such interfaces that would appear in the design according to configuration that user has done. For example, if a user has selected number of debug cores is 3, then only S00_AXIS and M00_AXIS, S01_AXIS and M01_AXIS, S02_AXIS and M02_AXIS would appear in the IP.

For detailed information of the signals in the AXI as well as AXI4-Stream interfaces, refer to the AXI protocol specification document mentioned in Vivado Design Suite: AXI Reference Guide (UG1037).