The AXI Debug Hub core allows for the host run-time software (such as Vivado Hardware Manager) to communicate and interact with debug cores and features within Versal devices. It provides an interface between the debug interface of the Versal device (such as JTAG or HSDP) and the debug cores within the Programmable Logic (PL) design.
The debug cores are directly attached to the Debug Hub core AXIS interfaces. However, Debug Hub uses an AXI interface to connect to Network-on-Chip (NoC) of Versal devices or General Purpose (GP) ports of the Processing System (PS). Once generated, the Debug Hub core is easily instantiated or added to the design.