The functional block diagram of the core is shown in Figure 1.
The AXI4 interface on the input side of the block diagram gives visibility to address spaces of the individual cores, along with a few debug hub registers. This approach requires understanding of the debug core's register space that is connected to the debug hub. The host must write the address register with a particular debug core register's offset address, and the content of the address must be updated by writing to the data registers.
The AXI4 Debug Hub has an AXI4 interface allowing connection to the control, interface, and processing system through a PS-PL interface or Network-on-Chip AXI4 master. The AXI4 Debug Hub also contains a configurable number of AXI4-Stream interfaces for connectivity to debug cores, such as VIO or ILA. The default configuration contains no AXI4-Stream masters or slaves allowing the core to be dynamically configured to the appropriate number of interfaces required and connected automatically to each debug core in the design.
Any reading in these registers generates a sequence of AXI4-Stream packets from the debug hub towards the debug cores with information from the address register and data registers. The response packet from the debug cores are accumulated and sent to the host over AXI4 interface.