Customizing and Generating the Core - 1.0 English

This section includes information about using Xilinx® tools to customize and generate the core in the Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

To access the BSCAN to JTAG Converter core, perform the following:

1. Open a project by selecting File > Open Project or create a new project by selecting File > New Project.
2. Open the IP catalog and navigate to Debug & Verification > Debug.
3. Double-click BSCAN to JTAG Converter to bring up the BSCAN to JTAG Customize IP dialog box as shown in the following figure:
   Figure 1. BSCAN to JTAG Core View in IP Catalog

The following figure shows the BSCAN to JTAG Customize IP dialog box with information about customizing ports. A configurable parameter is shown named as enable_tck_bufg that enables a buffer on the clock path of JTAG output.

Component Name

The Component Name field consists of any combination of alpha-numeric characters including the underscore symbol. However, the underscore symbol cannot be the first character in the component name.

Enable tck bufg

This user parameter is enabled only if a BUFG is required for tck in high speed applications.