Configuring the HBM - 1.0 English

DPUCAHX8L for Convolutional Neural Networks Product Guide (PG366)
Document ID
PG366
Release Date
2024-03-25
Version
1.0 English
The AMD Alveo™ U50, U50LV, U55C, and U280 cards support HBM. This section describes how to customize the HBM IP to meet DPU requirements and improve performance.

Although each AXI port connected to the HBM controller (HMSS) can access all the DDR memory addresses within the HBM, care is needed to minimize the horizontal traffic inside the HBM switch. This is accomplished by using the HBM AXI port that is vertically aligned with the HBM pseudo-channel (PC). Alternatively, the neighboring pseudo-channel connected to the same memory controller (MC) can be used (see HBM Configuration and Use in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393), example: AXI port 26 is associated with MC13, which can access PC26 and PC27). To achieve highest access performance, each feature map AXI port must be constrained to an appropriate pseudo-channel by way of the port constraint to avoid latency caused by inefficient horizontal access.

To configure the HBM, follow these steps:

  1. Add the system ports (sp) constraints to the cons.ini file.
    Note: In this example, the connectivity of each AXI port covers the full HBM-range access (HBM[00:31]), which does not resolve the horizontal traffic issue. Recommended connections can be found in the Making HBM Connections section of this document.)
    [connectivity]
nk=DPUCAHX8L_A:1:DPUCAHX8L_A
sp=DPUCAHX8L_A.DPU_VB_M_AXI_00:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_01:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_02:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_03:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_04:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_05:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_06:HBM[00:31]
sp=DPUCAHX8L_A.DPU_VB_M_AXI_07:HBM[00:31]
sp=DPUCAHX8L_A.DPU_SYS_M_AXI_00:HBM[00:31]
sp=DPUCAHX8L_A.DPU_SYS_M_AXI_01:HBM[00:31]
sp=DPUCAHX8L_A.DPU_SYS_M_AXI_02:HBM[00:31]
nk=DPUCAHX8L_B:1:DPUCAHX8L_B
sp=DPUCAHX8L_B.DPU_VB_M_AXI_00:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_01:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_02:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_03:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_04:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_05:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_06:HBM[00:31]
sp=DPUCAHX8L_B.DPU_VB_M_AXI_07:HBM[00:31]
sp=DPUCAHX8L_B.DPU_SYS_M_AXI_00:HBM[00:31]
sp=DPUCAHX8L_B.DPU_SYS_M_AXI_01:HBM[00:31]
sp=DPUCAHX8L_B.DPU_SYS_M_AXI_02:HBM[00:31]
  2. Use the --config "cons.ini" command to the v++ command.
  3. Set the corresponding connections to HBM Memory Sub-System (HMSS) and set the host_port address range (S00_MEM). Include all the memory ranges that are used in the sys_link_post.tcl.
  4. Put the following code at sys_link_post.tcl for one core: 
    hbm_memory_subsystem::force_host_port 28 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_00] 0 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_01] 1 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_02] 2 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_03] 3 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_04] 4 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_05] 5 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_06] 6 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_07] 7 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_00] 29 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_01] 24 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_02] 25 1 [get_bd_cells hmss_0]

set ap [get_property CONFIG.ADVANCED_PROPERTIES [get_bd_cells /hmss_0]]
dict set ap minimal_initial_configuration true
set_property CONFIG.ADVANCED_PROPERTIES $ap [get_bd_cells /hmss_0]

set_param bd.hooks.addr.debug_scoped_use_ms_name true
assign_bd_address [get_bd_addr_segs {DPUCAHX8L_A/s_axi_control/reg0 }]

    For two cores, use the following code:

    hbm_memory_subsystem::force_host_port 28 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_00]  0 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_01]  2 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_02]  1 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_03]  3 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_04]  4 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_05]  7 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_06]  5 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_VB_M_AXI_07]  6 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_00]  26 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_01]  24 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_A/DPU_SYS_M_AXI_02]  25 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_00]  8 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_01]  10 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_02]  9 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_03]  11 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_04]  12 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_05]  15 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_06]  13 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_VB_M_AXI_07]  14 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_SYS_M_AXI_00]  27 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_SYS_M_AXI_01]  22 1  [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /DPUCAHX8L_B/DPU_SYS_M_AXI_02]  23 1  [get_bd_cells hmss_0]

set ap [get_property CONFIG.ADVANCED_PROPERTIES [get_bd_cells /hmss_0]]
dict set ap minimal_initial_configuration true                                                                                                                                                                                           set_property CONFIG.ADVANCED_PROPERTIES $ap [get_bd_cells /hmss_0]

set_param bd.hooks.addr.debug_scoped_use_ms_name true
assign_bd_address [get_bd_addr_segs {DPUCAHX8L_A/s_axi_control/reg0 }]
assign_bd_address [get_bd_addr_segs {DPUCAHX8L_B/s_axi_control/reg0 }]
validate_bd_design -force

validate_bd_design -force
  5. Add the following lines to the cons.ini file.
    [advanced]
param=compiler.userPostSysLinkTcl=*/sys_link_post.tcl