DPU Configuration Registers - 1.0 English

DPUCAHX8L for Convolutional Neural Networks Product Guide (PG366)
Document ID
PG366
Release Date
2024-03-25
Version
1.0 English

The DPU configuration registers are used to indicate instruction address, common address and mean value settings.

The reg_instr_addr register is used to indicate the instruction address of the DPU core.

The reg_base_addr register is used to indicate the address of input image and parameters for the DPU in external memory. The width of a DPU base address is 34 bits supporting an address space up to 16 GB. All registers are 32-bit wide, thus, two registers are required to represent a 34-bit wide base address. The reg_base_addr0_l register represents the lower 32 bits of base_address0, and reg_base_addr0_h represents the upper 1 bit of base_address0. There are eight groups of DPU base address.

The details of configuration registers are shown in the following figure.

Table 1. DPU Configuration Registers
Register Address Offset Width Type Description
reg_base_addr_0_l 0x100 32 r/w The lower 32 bits of base address0 of DPU. 4 KB aligned.
reg_base_addr_0_h 0x104 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address0 of DPU.
reg_base_addr_1_l 0x108 32 r/w The lower 32 bits of base address1 of DPU. 4 KB aligned.
reg_base_addr_1_h 0x10c 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address1 of DPU.
reg_base_addr_2_l 0x110 32 r/w The lower 32 bits of base address2 of DPU. 4 KB aligned.
reg_base_addr_2_h 0x114 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address2 of DPU.
reg_base_addr_3_l 0x118 32 r/w The lower 32 bits of base address3 of DPU. 4 KB aligned.
reg_base_addr_3_h 0x11c 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address3 of DPU.
reg_base_addr_4_l 0x120 32 r/w The lower 32 bits of base address4 of DPU. 4 KB aligned.
reg_base_addr_4_h 0x124 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address4 of DPU.
reg_base_addr_5_l 0x128 32 r/w The lower 32 bits of base address5 of DPU. 4 KB aligned.
reg_base_addr_5_h 0x12c 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address5 of DPU.
reg_base_addr_6_l 0x130 32 r/w The lower 32 bits of base address6 of DPU. 4 KB aligned.
reg_base_addr_6_h 0x134 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address6 of DPU.
reg_base_addr_7_l 0x138 32 r/w The lower 32 bits of base address7 of DPU. 4 KB aligned.
reg_base_addr_7_h 0x13c 32 r/w The lower 1-bit in the register represent the upper 1-bit of base address7 of DPU.
reg_instr_addr_l 0x140 32 r/w The lower 32 bits of instruction address of DPU. 4 KB aligned.
reg_instr_addr_h 0x144 32 r/w The lower 1-bit in the register represent the upper 1-bit of instruction address of DPU. 4 KB aligned.