Although each AXI port connected to the HBM controller (HMSS) can access all the DDR memory addresses within the HBM, care is needed to minimize the horizontal traffic inside the HBM switch. This is accomplished by using the HBM AXI port that is vertically aligned with the HBM pseudo-channel (PC). Alternatively, the neighboring pseudo-channel connected to the same memory controller (MC) can be used (see HBM Configuration and Use in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393), example: AXI port 26 is associated with MC13, which can access PC26 and PC27). To achieve highest access performance, each feature map AXI port must be constrained to an appropriate pseudo-channel by way of the port constraint to avoid latency caused by inefficient horizontal access.
To configure the HBM, follow these steps:
- Add the system ports (sp) constraints to the cons.ini file. Note: In this example, the connectivity of each AXI port covers the full HBM-range access (HBM[00:31]), which does not resolve the horizontal traffic issue. Recommended connections can be found in the Making HBM Connections section of this document.)
[connectivity] nk=DPUCAHX8H_5ENGINE:1:dpu_0 nk=DPUCAHX8H_5ENGINE:1:dpu_1 sp=dpu_0.DPU_AXI_0:HBM[00:31] sp=dpu_0.DPU_AXI_1:HBM[00:31] sp=dpu_0.DPU_AXI_4:HBM[00:31] sp=dpu_1.DPU_AXI_0:HBM[00:31] sp=dpu_1.DPU_AXI_1:HBM[00:31] sp=dpu_1.DPU_AXI_4:HBM[00:31] sp=dpu_0.DPU_AXI_I0:HBM[00:31] sp=dpu_1.DPU_AXI_I0:HBM[00:31] sp=dpu_0.DPU_AXI_2:HBM[00:31] sp=dpu_0.DPU_AXI_3:HBM[00:31] sp=dpu_1.DPU_AXI_2:HBM[00:31] sp=dpu_1.DPU_AXI_3:HBM[00:31] sp=dpu_0.DPU_AXI_W0:HBM[00:31] sp=dpu_0.DPU_AXI_W1:HBM[00:31] sp=dpu_1.DPU_AXI_W0:HBM[00:31] sp=dpu_1.DPU_AXI_W1:HBM[00:31] - Use the
--config "cons.ini"command to the v++ command. - Put the following code at sys_link_post.tcl for one
core:
hbm_memory_subsystem::force_host_port 28 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_0] 0 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_1] 1 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_4] 2 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_0] 3 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_1] 4 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_4] 5 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_I0] 6 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_I0] 7 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_2] 16 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_3] 17 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_2] 18 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_3] 19 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_W0] 20 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_W1] 21 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_W0] 22 1 [get_bd_cells hmss_0] hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_W1] 23 1 [get_bd_cells hmss_0] - Add the following lines to the cons.ini
file.
[advanced] param=compiler.userPostSysLinkTcl=*/sys_link_post.tcl