DPU Configuration Registers - 1.2 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

Document ID
PG367
Release Date
2022-06-15
Version
1.2 English

The DPU configuration registers are used to indicate instruction address, common address and mean value settings.

The reg_instr_addr register is used to indicate the instruction address of the DPU core.

The reg_base_addr register is used to indicate the address of input image and parameters for the DPU in external memory. The width of a DPU base address is 34 bits supporting an address space up to 16 GB. All registers are 32-bit wide, thus, two registers are required to represent a 34-bit wide base address. The reg_base_addr0_l register represents the lower 32 bits of base_address0 in DPU core0, and reg_base_addr0_h represents the upper 2 bits of base_address0. There are eight groups of DPU base addresses for each DPU core, and therefore there are 40 groups of DPU base addresses for up to five DPU cores.

The details of configuration registers are shown in the following figure.

Table 1. DPU Configuration Registers
Register Address Offset Width Type Description
reg_instr_addr_l 0x140 32 r/w The lower 32 bits of instruction address of DPU. 4 KB aligned.
reg_instr_addr_h 0x144 32 r/w The lower two bits in the register represent the upper two bits of instruction address of DPU. 4 KB aligned.
reg_engine0_base_addr_0_l 0x100 32 r/w The lower 32 bits of base address0 of DPU engine0.
reg_engine0_base_addr_0_h 0x104 32 r/w The lower two bits in the register represent the upper two bits of base address0 of DPU engine0.
reg_engine0_base_addr_1_l 0x108 32 r/w The lower 32 bits of base address1 of DPU engine0.
reg_engine0_base_addr_1_h 0x10c 32 r/w The lower two bits in the register represent the upper two bits of base address1 of DPU engine0.
reg_engine0_base_addr_2_l 0x110 32 r/w The lower 32 bits of base address2 of DPU engine0.
reg_engine0_base_addr_2_h 0x114 32 r/w The lower two bits in the register represent the upper two bits of base address2 of DPU engine0.
reg_engine0_base_addr_3_l 0x118 32 r/w The lower 32 bits of base address3 of DPU engine0.
reg_engine0_base_addr_3_h 0x11c 32 r/w The lower two bits in the register represent the upper two bits of base address3 of DPU engine0.
reg_engine0_base_addr_4_l 0x120 32 r/w The lower 32 bits of base address4 of DPU engine0.
reg_engine0_base_addr_4_h 0x124 32 r/w The lower two bits in the register represent the upper two bits of base address4 of DPU engine0.
reg_engine0_base_addr_5_l 0x128 32 r/w The lower 32 bits of base address5 of DPU engine0.
reg_engine0_base_addr_5_h 0x12c 32 r/w The lower two bits in the register represent the upper two bits of base address5 of DPU engine0.
reg_engine0_base_addr_6_l 0x130 32 r/w The lower 32 bits of base address6 of DPU engine0.
reg_engine0_base_addr_6_h 0x134 32 r/w The lower two bits in the register represent the upper two bits of base address6 of DPU engine0.
reg_engine0_base_addr_7_l 0x138 32 r/w The lower 32 bits of base address7 of DPU engine0.
reg_engine0_base_addr_7_h 0x13c 32 r/w The lower two bits in the register represent the upper two bits of base address7 of DPU engine0.
reg_engine1_base_addr_0_l 0x200 32 r/w The lower 32 bits of base address0 of DPU engine1.
reg_engine1_base_addr_0_h 0x204 32 r/w The lower two bits in the register represent the upper two bits of base address0 of DPU engine1.
reg_engine1_base_addr_1_l 0x208 32 r/w The lower 32 bits of base address1 of DPU engine1.
reg_engine1_base_addr_1_h 0x20c 32 r/w The lower 2-bit in the register represent the upper 2-bit of base address1 of DPU engine1.
reg_engine1_base_addr_2_l 0x210 32 r/w The lower 32 bits of base address2 of DPU engine1.
reg_engine1_base_addr_2_h 0x214 32 r/w The lower two bits in the register represent the upper two bits of base address2 of DPU engine1.
reg_engine1_base_addr_3_l 0x218 32 r/w The lower 32 bits of base address3 of DPU engine1.
reg_engine1_base_addr_3_h 0x21c 32 r/w The lower two bits in the register represent the upper two bits of base address3 of DPU engine1.
reg_engine1_base_addr_4_l 0x220 32 r/w The lower 32 bits of base address4 of DPU engine1.
reg_engine1_base_addr_4_h 0x224 32 r/w The lower two bits in the register represent the upper two bits of base address4 of DPU engine1.
reg_engine1_base_addr_5_l 0x228 32 r/w The lower 32 bits of base address5 of DPU engine1.
reg_engine1_base_addr_5_h 0x22c 32 r/w The lower two bits in the register represent the upper two bits of base address5 of DPU engine1.
reg_engine1_base_addr_6_l 0x230 32 r/w The lower 32 bits of base address6 of DPU engine1.
reg_engine1_base_addr_6_h 0x234 32 r/w The lower two bits in the register represent the upper two bits of base address6 of DPU engine1.
reg_engine1_base_addr_7_l 0x238 32 r/w The lower 32 bits of base address7 of DPU engine1.
reg_engine1_base_addr_7_h 0x23c 32 r/w The lower two bits in the register represent the upper two bits of base address7 of DPU engine1.
reg_engine2_base_addr_0_l 0x300 32 r/w The lower 32 bits of base address0 of DPU engine2.
reg_engine2_base_addr_0_h 0x304 32 r/w The lower two bits in the register represent the upper two bits of base address0 of DPU engine2.
reg_engine2_base_addr_1_l 0x308 32 r/w The lower 32 bits of base address1 of DPU engine2.
reg_engine2_base_addr_1_h 0x30c 32 r/w The lower two bits in the register represent the upper two bits of base address1 of DPU engine2.
reg_engine2_base_addr_2_l 0x310 32 r/w The lower 32 bits of base address2 of DPU engine2.
reg_engine2_base_addr_2_h 0x314 32 r/w The lower two bits in the register represent the upper two bits of base address2 of DPU engine2.
reg_engine2_base_addr_3_l 0x318 32 r/w The lower 32 bits of base address3 of DPU engine2.
reg_engine2_base_addr_3_h 0x31c 32 r/w The lower 2-bit in the register represent the upper 2-bit of base address3 of DPU engine2.
reg_engine2_base_addr_4_l 0x320 32 r/w The lower 32 bits of base address4 of DPU engine2.
reg_engine2_base_addr_4_h 0x324 32 r/w The lower two bits in the register represent the upper two bits of base address4 of DPU engine2.
reg_engine2_base_addr_5_l 0x328 32 r/w The lower 32 bits of base address5 of DPU engine2.
reg_engine2_base_addr_5_h 0x32c 32 r/w The lower 2-bit in the register represent the upper 2-bit of base address5 of DPU engine2.
reg_engine2_base_addr_6_l 0x330 32 r/w The lower 32 bits of base address6 of DPU engine2.
reg_engine2_base_addr_6_h 0x334 32 r/w The lower two bits in the register represent the upper two bits of base address6 of DPU engine2.
reg_engine2_base_addr_7_l 0x338 32 r/w The lower 32 bits of base address7 of DPU engine2.
reg_engine2_base_addr_7_h 0x33c 32 r/w The lower two bits in the register represent the upper two bits of base address7 of DPU engine2.
reg_engine3_base_addr_0_l 0x400 32 r/w The lower 32 bits of base address0 of DPU engine3.
reg_engine3_base_addr_0_h 0x404 32 r/w The lower two bits in the register represent the upper two bits of base address0 of DPU engine3.
reg_engine3_base_addr_1_l 0x408 32 r/w The lower 32 bits of base address1 of DPU engine3.
reg_engine3_base_addr_1_h 0x40c 32 r/w The lower two bits in the register represent the upper two bits of base address1 of DPU engine3.
reg_engine3_base_addr_2_l 0x410 32 r/w The lower 32 bits of base address2 of DPU engine3.
reg_engine3_base_addr_2_h 0x414 32 r/w The lower two bits in the register represent the upper two bits of base address2 of DPU engine3.
reg_engine3_base_addr_3_l 0x418 32 r/w The lower 32 bits of base address3 of DPU engine3.
reg_engine3_base_addr_3_h 0x41c 32 r/w The lower two bits in the register represent the upper two bits of base address3 of DPU engine3.
reg_engine3_base_addr_4_l 0x420 32 r/w The lower 32 bits of base address4 of DPU engine3.
reg_engine3_base_addr_4_h 0x424 32 r/w The lower two bits in the register represent the upper two bits of base address4 of DPU engine3.
reg_engine3_base_addr_5_l 0x428 32 r/w The lower 32 bits of base address5 of DPU engine3.
reg_engine3_base_addr_5_h 0x42c 32 r/w The lower two bits in the register represent the upper two bits of base address5 of DPU engine3.
reg_engine3_base_addr_6_l 0x430 32 r/w The lower 32 bits of base address6 of DPU engine3.
reg_engine3_base_addr_6_h 0x434 32 r/w The lower two bits in the register represent the upper two bits of base address6 of DPU engine3.
reg_engine3_base_addr_7_l 0x438 32 r/w The lower 32 bits of base address7 of DPU engine3.
reg_engine3_base_addr_7_h 0x43c 32 r/w The lower two bits in the register represent the upper two bits of base address7 of DPU engine3.
reg_engine4_base_addr_0_l 0x500 32 r/w The lower 32 bits of base address0 of DPU engine4.
reg_engine4_base_addr_0_h 0x504 32 r/w The lower two bits in the register represent the upper two bits of base address0 of DPU engine4.
reg_engine4_base_addr_1_l 0x508 32 r/w The lower 32 bits of base address1 of DPU engine4.
reg_engine4_base_addr_1_h 0x50c 32 r/w The lower two bits in the register represent the upper two bits of base address1 of DPU engine4.
reg_engine4_base_addr_2_l 0x510 32 r/w The lower 32 bits of base address2 of DPU engine4.
reg_engine4_base_addr_2_h 0x514 32 r/w The lower two bits in the register represent the upper two bits of base address2 of DPU engine4.
reg_engine4_base_addr_3_l 0x518 32 r/w The lower 32 bits of base address3 of DPU engine4.
reg_engine4_base_addr_3_h 0x51c 32 r/w The lower two bits in the register represent the upper two bits of base address3 of DPU engine4.
reg_engine4_base_addr_4_l 0x520 32 r/w The lower 32 bits of base address4 of DPU engine4.
reg_engine4_base_addr_4_h 0x524 32 r/w The lower two bits in the register represent the upper two bits of base address4 of DPU engine4.
reg_engine4_base_addr_5_l 0x528 32 r/w The lower 32 bits of base address5 of DPU engine4.
reg_engine4_base_addr_5_h 0x52c 32 r/w The lower two bits in the register represent the upper two bits of base address5 of DPU engine4.
reg_engine4_base_addr_6_l 0x530 32 r/w The lower 32 bits of base address6 of DPU engine4.
reg_engine4_base_addr_6_h 0x534 32 r/w The lower two bits in the register represent the upper two bits of base address6 of DPU engine4.
reg_engine4_base_addr_7_l 0x538 32 r/w The lower 32 bits of base address7 of DPU engine4.
reg_engine4_base_addr_7_h 0x53c 32 r/w The lower two bits in the register represent the upper two bits of base address7 of DPU engine4.