DPU Signals - 1.2 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

Document ID
PG367
Release Date
2022-06-15
Version
1.2 English

The following table lists the DPU I/O signals and their function descriptions.

Table 1. DPU Signals
Signal Name Interface Type Width I/O Description
s_axi_control Memory mapped AXI slave interface 32 I/O 32-bit memory mapped AXI interface for registers.
ap_clk Clock 1 I Kernel clock. The frequency of the clock should match the clock of the DPU core. The supported frequencies are 300 MHz, 275 MHz, and 250 MHz.
ap_clk_2 Clock 1 I Reference clock for the MMCM in the DPU. It is set to 100 MHz.
ap_rst_n Reset 1 I Active-Low reset for DPU general logic.
ap_rst_n_2 Reset 1 I Unused in the core.
DPU_AXI_0 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU engine0.
DPU_AXI_1 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU engine1.
DPU_AXI_2 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU engine2.
DPU_AXI_3 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU engine3.
DPU_AXI_4 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU engine4.
DPU_AXI_I Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU instructions.
DPU_AXI_W0 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
DPU_AXI_W1 Memory mapped AXI master interface 256 I/O 256-bit memory mapped AXI interface for DPU parameters.
interrupt Interrupt 1 O Active-High interrupt output from the DPU.
  1. The DPU_AXI_3~ DPU_AXI_4 interfaces are only present when a three or four engine DPU is used.