DPU cores work synchronously, all DPU engines generate an interrupt to signal
the completion of a task. A high state on
the start of a DPU task. At the end of the task, the DPU generates an
interrupt and bit0 in IPISR and
set to 1.
To support DPU interrupt, the DPU implements the following registers:
- Global Interrupt Enable Register (GIER)
- Provides the master enable/disable for the interrupt output to the processor or Interrupt Controller. See Global Interrupt Enable Register (GIER) in Table 1 for more details.
- IP Interrupt Enable Register (IPIER)
- Implements the independent interrupt enable bit for each channel. See IP Interrupt Enable (IPIER) and IP Status Registers (IPISR) in Table 1 for more details.
- IP Interrupt Status Register (IPISR)
- Implements the independent interrupt status bit for each channel. The IPISR provides Read and Toggle-On-Write access. The Toggle-On-Write mechanism allows interrupt service routines to clear one or more ISR bits using a single write transaction. The IPISR can also be manually set to generate an interrupt for testing purposes. See IP Interrupt Enable (IPIER) and IP Status Registers (IPISR) in Table 1 for additional details.