Making HBM Connections - 1.2 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

Document ID
PG367
Release Date
2022-06-15
Version
1.2 English

DPUCAHX8H can be deployed with one or two cores on the Alveo U50/U50LV card or with one, two, or three cores on the Alveo U280/U55C card. They are named core0, core1, and core2. You can locate core0 on SLR0, core1 on SLR1, and core2 on SLR2. To get the best performance of HBM, DPU AXI ports should be connected with the following rules.

Table 1. core0 HBM Port Connections
DPU AXI Interfaces HBM AXI Interfaces
DPU_AXI_0 AXI_00
DPU_AXI_1 AXI_01
DPU_AXI_2 AXI_02
DPU_AXI_3 AXI_03 (unused if PE number <4)
DPU_AXI_4 AXI_04 (unused if PE number <5)
DPU_AXI_I AXI_05
DPU_AXI_W0 AXI_06
DPU_AXI_W1 AXI_07
Table 2. core1 HBM Port Connections
DPU AXI Interfaces HBM AXI Interfaces
DPU_AXI_0 AXI_08
DPU_AXI_1 AXI_09
DPU_AXI_2 AXI_10
DPU_AXI_3 AXI_11 (unused if PE number <4)
DPU_AXI_4 AXI_12 (unused if PE number <5)
DPU_AXI_I AXI_13
DPU_AXI_W0 AXI_14
DPU_AXI_W1 AXI_15
Table 3. core2 HBM Port Connections
DPU AXI Interfaces HBM AXI Interfaces
DPU_AXI_0 AXI_16
DPU_AXI_1 AXI_17
DPU_AXI_2 AXI_18
DPU_AXI_3 AXI_19 (unused if PE number <4)
DPU_AXI_4 AXI_20 (unused if PE number <5)
DPU_AXI_I AXI_21
DPU_AXI_W0 AXI_22
DPU_AXI_W1 AXI_23