AXI4-Stream Interface Signaling - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English
Note: In these tables, <N> = port number 0-5 and <M> is the segment number 0 to 11.
Table 1. Segmented AXI4-Stream Interface Signal Descriptions: TX Direction
Port Name Clock Domain I/O Description
tx_axis_tready_<N> tx_axi_clk O AXI TREADY. Asserted to indicate acceptance of data.
tx_axis_taf_<N> tx_axi_clk O Almost full indicator. Provided as an advance warning that _tready will be de-asserted if there is no break in incoming client data.
tx_axis_ch_status_vld tx_axi_clk O Validation signal for the Channel Status bus; only used in independent mode
tx_axis_ch_status_id[5:0] tx_axi_clk O Channel ID
tx_axis_ch_status_skip_req tx_axi_clk O Indicates that the internal time-sliced MAC requires an active skip response
tx_axis_tuser_skip_response tx_axi_clk I Asserted to indicate that returning cycle is a skip response
tx_axis_id_req_vld tx_axi_clk O Validates tx_axis_id_req
tx_axis_id_req[5:0] tx_axi_clk O Request Channel ID that needs to be returned (on tx_axis_tid) by client in independent mode
tx_axis_tvalid_<N> tx_axi_clk I Valid signal for the AXI bus
tx_axis_tid[5:0] tx_axi_clk I Channel ID for client transaction. Only used in Indendent Mode
tx_preamblein_<N>[55:0] tx_axi_clk I TX packet preamble
tx_ptp_cf_offset_in_<N>[13:0] tx_axi_clk I Packet offset, in octets, to the beginning of the correction field in the PTP packet. Maximum value of 16304 decimal.
tx_ptp_tag_field_in_<N>[7:0] tx_axi_clk I Unique identifier for PTP packet which can be used to match TX timestamps with a specific packet. This tag will be returned on tx_ptp_tag_out.
tx_ptp_udp_chksum_in_<N> tx_axi_clk I Enable UDP checksum processing on 1-step PTP packets
tx_ptp_1588op_in_<N>[1:0] tx_axi_clk I

2'b00: No operation: no timestamp is taken and the frame is not modified.

Bit 0: "1-step": a timestamp should be taken and inserted into the frame.

Bit 1: "2-step": a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself is not modified.

tx_axis_tdata<M>[127:0] tx_axi_clk I AXI Data
tx_axis_tuser_ena<M> tx_axi_clk I Segment enable; deasserted to indicate per-segment IDLE
tx_axis_tuser_sop<M> tx_axi_clk I Segment Start-of-Packet indicator; only valid for enabled segments
tx_axis_tuser_eop<M> tx_axi_clk I Segment End-of-Packet indicator; only valid for enabled segments
tx_axis_tuser_err<M> tx_axi_clk I Segment Error indicator
tx_axis_tuser_mty<M>[3:0] tx_axi_clk I Segment Empty Bytes indicator; only valid for enabled EOP segments
Table 2. Segmented AXI4-Stream Interface Signal Descriptions: RX Direction
Port Name Clock Domain I/O Description
rx_axis_tvalid_<N> rx_axi_clk O Standard AXI valid; validates entire rx_axis_ bus
rx_axis_tid[5:0] rx_axi_clk O Channel ID
rx_preambleout_<N>[55:0] rx_axi_clk O RX packet preamble
rx_ptp_tstamp_out_<N>[31:0] rx_axi_clk O Timestamp of the PTP packet with 2-8 ns granularity.
Note: The upper bits have been omitted to reduce the number of output pins.
rx_axis_tdata<M>[127:0] rx_axi_clk O AXI data
rx_axis_tuser_ena<M> rx_axi_clk O Per-segment enable
rx_axis_tuser_sop<M> rx_axi_clk O Segment Start-of-Packet indicator; only valid for enabled segments
rx_axis_tuser_eop<M> rx_axi_clk O Segment End-of-Packet indicator; only valid for enabled segments
rx_axis_tuser_err<M> rx_axi_clk O Segment Error indicator
rx_axis_tuser_mty<M>[3:0] rx_axi_clk O Segment Empty Bytes indicator; only valid for enabled EOP segments