AXI4-Stream for Coupled MAC+PCS Mode - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

Coupled MAC+PCS mode is often called standard Fixed Ethernet (FixedE) mode. When configured in this mode, the AXI4-Stream interface operates in non-channelized segmented mode that ensures high throughput over a range of traffic profiles. The interface is dynamically reconfigurable during runtime to support multiple modes of Ethernet operation. The DCMAC Subsystem AXI4-Stream interface supports up to a total of 600 Gbps bandwidth. It can be configured as six independent 100 Gbps AXI4-Stream interfaces. Alternatively, the portions of the AXI4-Stream interface can be ganged together to deliver individual AXI4-Stream interface rates of 200 Gbps or 400 Gbps, in addition to combinations of 100 Gbps, 200 Gbps and 400 Gbps.

The AXI4-Stream interface data rates are configured using the following fields:
  • The c0_ctl_tx_data_rate, c2_ctl_tx_data_rate, and c4_ctl_tx_data_rate fields of the C0_TX_MODE_REG, C2_TX_MODE_REG, and C4_TX_MODE_REG for TX.
  • The c0_ctl_rx_data_rate, c2_ctl_rx_data_rate, and c4_ctl_rx_data_rate fields of the C0_RX_MODE_REG, C2_RX_MODE_REG, and C4_RX_MODE_REG registers for RX.
These can be configured dynamically, provided traffic is not flowing on the corresponding portions of the AXI4-Stream interface.

The AXI clock frequencies in the following table are required to meet bandwidth for a given Ethernet interface.

You can use a lower frequency AXI clock to ease timing closure in some device speed grades. To enable use of a reduced clock frequency, a special mode exists that doubles the width of each 100GE AXI4-Stream interface to 512 bits while reducing to three the number of distinct 100GE AXI4-Stream interfaces. This mode is entered using the control fields ctl_tx_axis_cfg and ctl_rx_axis_cfg of the GLOBAL_MODE register. In addition, the control fields ctl_tx_pcs_active_ports and ctl_rx_pcs_active_ports of the same register must be set appropriately.

Table 1. DCMAC Subsystem AXI4-Stream Configurations for Coupled MAC+PCS Mode
Data Rate Nominal Clock Frequency (MHz) AXI4-Stream Data Width (Bits) ctl_tx_axis_cfg / ctl_rx_axis_cfg c<N>_ctl_tx_data_rate / c<N>_ctl_rx_data_rate
N=0 N=2 N=4
6 x 100GE 390.625 6 x 256 0 2'b00 1'b0 1'b0
3 x 200GE 390.625 3 x 512 0 2'b01 1'b1 1'b1

1 x 400GE

1 x 200GE

390.625

1 x 1024

1 x 512

0 2'b10 N/A 1'b1

1 x 400GE

2 x 100GE

390.625

1 x 1024

2 x 256

0 2'b10 N/A 1'b0

1 x 200GE

4 x 100GE

390.625

1 x 512

4 x 256

0 2'b01 1'b0 1'b0
... ... ... ... ... ... ...
3 x 100GE 195.313 3 x 512 1 2'b00 1'b0 1'b0