Applications - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English
The DCMAC Subsystem is a highly flexible IEEE-designed network interface for applications that require a very high bit rate, such as:
  • Ethernet switches
  • IP routers
  • Data center switches
  • Communications equipment
The capability to interconnect devices at 50, 100, 200, and 400 Gbps Ethernet rates becomes especially relevant for next-generation data center networks where the following conditions might occur:
  • To keep up with increasing CPU and storage bandwidth, rack or blade servers must support aggregate throughputs faster than 50 Gbps (single lane) or 100 Gbps (dual lane) from their Network Interface Card or LAN-on-Motherboard (LOM) networking ports.
  • Given the increased bandwidth to endpoints, uplinks from Top-of-Rack (TOR) or Blade switches need to transition from 100 Gbps (four lanes) to 400 Gbps (four lanes) while ideally maintaining the same per-lane breakout capability.
  • Due to the expected adoption of 400GBASE-CR4/KR4/SR4/LR4, SerDes and cabling technologies are already being developed and deployed to support 100 Gbps per physical lane, twinax cable, or fiber.

In addition to typical Coupled MAC+PCS application for up to six ports (up to 12 ports for 50 Gbps FEC-only), the DCMAC Subsystem supports MAC client monitoring applications for up to 40 channels.

The DCMAC Subsystem provides support for OIF Flex Ethernet (FlexE) by exposing a channelized MAC interface (MAC I/F) that can be connected to the client side of a FlexE shim. Likewise, the DCMAC Subsystem flex interface (FLEX I/F) provides access to the PHYs and can be connected to the FlexE group side of a FlexE shim. The FlexE shim is implemented in user logic.

The DCMAC Subsystem supports ITU-T Flexible OTN (FlexO) through the FLEX I/F. This provides access to the FEC and lane deskew logic and includes support for additional deskew using alignment buffers in user logic.