Clocks - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID: PG369
Release Date: 2023-11-08
Version: 2.3 English

The following table lists the clocks that are present in the DCMAC Subsystem.

Table 1. Clocks
Clock	Port	Description	Nominal Frequency Range (MHz)¹	Overclocked Rate (MHz) Superscript²
AXI4-Lite	s_axi_clk	AXI4-Lite processor interface clock.	50 - 300	300
AXI	tx_axi_clk rx_axi_clk	AXI4-Stream interface clocks. These clocks are used by the AXI4-Stream interface. They are also used by a number of device statistics and flow control signals.	195.3125 - 390.625	415.2512
core	tx_core_clk rx_core_clk	High-speed clocks which drive internal core logic.	390.625 -782	830.502
serdes	tx_serdes_clk[5:0] rx_serdes_clk[5:0]	Per-port high-speed clocks for the GT interface.	644.5313 - 664.0625	705.25³
serdes	tx_serdes_clk[5:0] rx_serdes_clk[5:0]	Per-port high-speed clocks for the GT interface.	644.5313 - 664.0625	700⁴
alt_serdes	tx_alt_serdes_clk[5:0] rx_alt_serdes_clk[5:0]	Per-port alternate low-frequency clocks for the GT interface.	322.2656 - 332.0313	352.625³
alt_serdes	tx_alt_serdes_clk[5:0] rx_alt_serdes_clk[5:0]		322.2656 - 332.0313	350⁴
flexif	tx_flexif_clk[5:0] rx_flexif_clk[5:0]	Per-port FLEX I/F clocks.	312.50 - 390.625	427.4242
macif	tx_macif_clk rx_macif_clk	MAC I/F clocks.	260.4167 - 390.625	415.2512
ts	ts_clk[5:0]	Per-port clocks for the timestamp interface.	50 - 350	350.000
Across all operational modes of the DCMAC Subsystem. Required frequency depends on operational mode. The Overclocked Rate options are supported with -2 and higher speed grade devices. For transceiver lane serial rate up to 56.42 Gbps. For transceiver lane serial rate beyond 56.52 Gbps and up to 112 Gbps.