This chapter explains the AMD Versal™ Adaptive SoC DCMAC Subsystem example design and various test scenarios implemented within the example design. The example design runs the packet generator to send a fixed number of packets to the TX AXI4-Stream interface and then monitors the logic read statistics to confirm if a packet was received successfully.
For the DCMAC Subsystem example design, the GT subcore is always in the example design. This example design demonstrates fixed speeds 6x100GE CAUI-4, 6x100GE 100GAUI-4, 3x200GE 200GAUI-8, and 1x400GE 400GAUI-16 configurations with GTYP and GTM NRZ support. The example design demonstrates fixed speeds of 6x100GE 100GAUI-2, 3x200GE 200GAUI-4, and 1x400GE 400GAUI-8 PAM4 configurations with GTM PAM4 support.