The flex interface (FLEX I/F) is a series of tap points along the PHY/FEC datapath that allows external logic to connect to the internal hardened PCS resources as a PCS client with a full PCS state machine, a raw, scrambled PCS client (for example, transparent OTN mapping), or an unscrambled PCS with optional error block replacement (for example, FlexE mapping). 128GFC is also supported, along with direct access to the on-board FEC resources (including support for FlexO). The following diagram illustrates RX and TX functions in the path between the PCS lane alignment logic to the FLEX I/F port.
To support the multiple applications, each flex interface port has logic, and corresponding controls to enable/disable the descramble/scramble logic, alignment insertion/removal logic, invalid sync-header error block replacement, and PCS encoder/decoder logic.