Memory Map - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The AXI4-Lite interface enables access to the DCMAC Subsystem configuration and statistics registers. Each port has a set of independent configuration registers, status registers, and statistics counters.

When the MAC interface (MAC I/F) is enabled, a full set of per-channel configuration registers is available.

Table 1. DCMAC Memory Map
Port Channel Base Address Region
N/A N/A 0x0000 Revision Registers
N/A N/A 0x0004 Global Configuration and Status Registers
0 0 0x1000 Port 0 / Channel 0 Configuration Registers
0 0 0x1100 Port 0 / Channel 0 Status Registers and Statistics Counters
1 1 0x2000 Port 1 / Channel 1 Configuration Registers
1 1 0x2100 Port 1 / Channel 1 Status Registers and Statistics Counters
2 2 0x3000 Port 2 / Channel 2 Configuration Registers
2 2 0x3100 Port 2 / Channel 2 Status Registers and Statistics Counters
3 3 0x4000 Port 3 / Channel 3 Configuration Registers
3 3 0x4100 Port 3 / Channel 3 Status Registers and Statistics Counters
4 4 0x5000 Port 4 / Channel 4 Configuration Registers
4 4 0x5100 Port 4 / Channel 4 Status Registers and Statistics Counters
5 5 0x6000 Port 5 / Channel 5 Configuration Registers
5 5 0x6100 Port 5 / Channel 5 Status Registers and Statistics Counters
N/A 6 0x7000 Channel 6 Configuration Registers
N/A 7 0x8000 Channel 7 Configuration Registers
... ... ... ...
N/A ID 0x1000 + ID * 0x1000 Channel 'ID' Configuration Registers
... ... ... ...
N/A 38 0x27000 Channel 38 Configuration Registers
N/A 39 0x28000 Channel 39 Configuration Registers