RS-FEC Statistics TDM Interface - 2.3 English

This TDM interface is used to report a subset of FEC statistics on a per codeword basis. This is provided in addition to the internal registers and PCS TDM information, both of which gather information over time and therefore lack the codeword-by-codeword data that might be needed for some applications. This interface is provided exclusively in the receive direction and consists of the following signals, all timed to the rx_axi_clk:

rx_rsfec_tdm_stats_data[15:0]

Statistics information.

rx_rsfec_tdm_stats_start

Indicates the start of a new TDM cycle.

rx_rsfec_tdm_stats_valid

Validates rx_rsfec_tdm_stats_data and rx_rsfec_tdm_stats_start.

The TDM interface starts (rx_rsfec_tdm_stats_valid and rx_rsfec_tdm_stats_start both asserted) with statistics for port 0, then port 1, and so on until port 5. It takes six rx_axi_clk cycles to loop through all the statistics. Individual ports do not necessarily always have updated statistics to relay; their slot in the six-cycle loop only indicates new (non-zero) information when a new FEC codeword has been received (valid remains asserted regardless).

Some Independent MAC and PCS+FEC mode applications might derate the rx_axi_clk to make use of a low bandwidth receive time-sliced MAC. Because this RS-FEC statistics TDM interface relies on rx_axi_clk, it is important to note that the clock must meet minimum thresholds to avoid a loss of information:

400G RS-FEC

rx_axi_clk must be at least 280 MHz.

128G FC RS-FEC

rx_axi_clk must be at least 150 MHz.

All other RS-FEC rates

rx_axi_clk must be at least 140 MHz.

Furthermore, proper operation of the RS-FEC Statistics TDM interface requires the existence of rx_core_clk. Thus, gating the rx_core_clk is prohibited when user logic is relying on information conveyed over the RS-FEC Statistics TDM interface.

The breakdown of the data bus into individual fields is described in the Register Space section.