Recognize Timing Critical Signals - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The constraints provided with the example design identify the critical signals and timing constraints that should be applied.