Register Space - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The DCMAC IP subsystem registers are accessible in a ZIP file. All registers are accessible through the AXI4-Lite interface.